Programmable logic devices (PLDs) are a type of programmable integrated circuit (IC) that can be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The programmable interconnect structure (also referred to as a routing fabric) typically includes conductors of various lengths interconnected by programmable switches (referred to as programmable routing resources). For example, some types of conductors may span two CLBs (referred to as doubles), while other types of conductors may span six CLBs (referred to as hexes). The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as an FPGA, has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them.
The stacked ICs are packaged in modules before they are bonded to a carrier such a printed circuit board. The module consists of one or more IC dice bonded to an interposer. One technique for connecting the IC dice to the interposer is thermal compression bonding. A single solder bump (e.g., a micro-bump) is deposited on each bond pad on the interposer to form the bonds between the IC die and the interposer. The IC die is pressed to the interposer by a thermal compression bonding tool and heat is applied to fuse the IC die to the interposer. Additional IC dice can also be connected to the interposer in the same manner. The IC package is then bonded to a carrier using, for example, the Controlled Collapse Chip Connection (C4) process. The above described types of bonding process are also often referred to as flip-chip bonding.
In order to improve bonding yield between the IC dice and the interposer in the flip-chip bonding process, redundant micro-bumps are added to the interposer for each pad on the IC dice. While the use of redundant micro-bumps improves bonding yield, it also increases area overhead due to the corresponding increase in the number of pads on the interposer needed for each of the redundant micro-bumps. For example, if a redundant micro-bump is used for each connection between the interposer and the IC dice, the area overheard increases linearly with the number of redundant micro-bumps. As such, the addition of redundant micro-bumps decreases the number of input/output connections that can be formed between the IC dice and the interposer.
The present invention may address one or more of the above issues.